Friday, November 25, 2005

Schematic update

Schematic finally updated...

-10uF Tant Caps added for decoupling
-Driver Buffers Changed to sn74ahc541
-SIL Resistors changed to DIL for ease of layout.
-Onboard crystals added, with jumpers for switching - can also be connected to switches for a frontpanel.

CPLD Research

Following some info from a few people on groupdiy (Designmasta and tmbg) I've had a look at the Xilinx range of CPLD's - and I must agree, for more advanced boards (i.e. a next generation board of this type?) then a cpld is a definite possibility.

I think the main use of a CPLD in a board of this type is more a routing matrix for now though, or possibly a routing matrix with some extra functions.

Programming them looks relatively simple (you need a parallel port on you're PC from the looks of things, and the right cable that comes with the $50 starter kit).

Anyway, I'm hoping to sit down tonight and do the schematic updates discussed.

Wednesday, November 23, 2005

Decisions based on feedback

Based on the feedback so far from MCS and Designmaster - these changes are to be made to the Schematic

Changes to make
  • Add 10uF Tant Capacitors to "high current" driver devices.
  • Convert the 4way output pins to 10way ribbon connectors using a DGND connection for every other pin. That will also allow me to send another clock derivative.
  • Add a "clock source select" section - allowing the user to select a 44.1KHz crystal circuit or 48KHz circuit.

Investigation to make

CPLD use for changing settings - how easy can it be? Is it within the grasp of the DIY'er?

Feedback on initial schematic

Good feedback today from both MCS and Designmaster on the initial schematic posted on

From Designmaster:
I would add a 10uF Tantalum capacitor for each device in parallel to the 100nF 8 buffers are a lot. typical 40pF load. You can also use ICS551 which is a 1 to 4 buffer, I know keep it easy. But it should work, you may have to play a little with the value of the serial resistor and the kind you distribute the signals on the PCB. Why don't you go for a FPGA or on the Wordclock board for a CPLD (XC9572XL)? Would make your life much easier and you can get ride of a lot of jumpers.

I only saw 100nF caps but by driving "heavy" loads where does the energy came from. First from the 100nF right but than?? You only have a 2 layer board and you will need at least 2 or better 3 of 10uF Tantalum. One right at the connector and the others around on the board.

From MCS:
Wordclock should be an Ethernet-like bus with T-connectors and a terminator at the end - but I don't know. You would need a terminator when the input is not used, but I guess most people have some Ethernet terminators available...

I'm not sure the four outputs need buffers - my board works fine without at least. But the bitclock, wordclock and masterclock do of course.

I normally like to put ground pins between the signals on the headers to keep them from interfering (a la SCSI). I actually use 10-pin connectors with a lot of ground pins. But that's mostly because cables with 10-pin IDC connectors are so easy to make.

Here's my tested OptoGen schematic BTW:

Tuesday, November 22, 2005


here's the first schematic - it still needs a lot of work though - any comments (corrections please!)


SN74ABT541B might be the driver i'm looking for :)

PCM4202 EVM Study

PCM4202 EVM users guide

I've been looking at this EVM to see how things are done on TI's EVM's - looking for good design guides.

100R Resistors on outputs:
It looks like there are 100 ohm resistors (in series, NOT tied to ground) on every logic device's output. This (according to MCS on Groupdiy) is for termination reasons and other factors.

Is used as a buffer/line driver for the 3.3V devices on the board.
For 5V devices

look to be good replacements, but they need to support up to 256fS (around 25MHz).

The CDC337 looks very interesting - it's a Clock driver that can support a single clock in, the 4 out, plus another 4 at half the rate. So if we take 256fS as one clock rate, we can get 128fS out as well.

More as I think of it. :)



ADAT Card and ADC

Ahhhh... let me see, where do I begin... This project is happening over at The actual thread is:
The Idea so far is:

Stereo ADC Card118dB 24bit, working either from onboard crystals to generate clocks to drive an S/PDIF Transmitter up to 96KHz or in a slave mode that will support up to 48KHz.Basically, it can act a standalone ADC with S/PDIF or as part of an ADAT 8 channel ADC.

Can generate all clocks from an external word clock or ADAT input. 4 connectors onboard to distribute clocks (Fs, 128fS and 256fS to the adc card) and bring back the Data from each of the stereo ADC's. The card will then convert the data from each stereo ADC into a single ADAT stream.

On the ADAT card there are 8 external 4 way connectors...
4x [data out, Wordclock, 256xWordclock and 64x Wordclock]
4x [data in, Wordclock, 256x Wordclock and 64x Wordclock]

Each of these are buffered for 5V use to go over 0.1" connectors to ADC cards or DAC cards.
The I/O on the ADAT card will be +5V - this should help with noise performance as well.