Feedback on initial schematic

Good feedback today from both MCS and Designmaster on the initial schematic posted on www.groupdiy.com

From Designmaster:
I would add a 10uF Tantalum capacitor for each device in parallel to the 100nF 8 buffers are a lot. typical 40pF load. You can also use ICS551 which is a 1 to 4 buffer, I know keep it easy. But it should work, you may have to play a little with the value of the serial resistor and the kind you distribute the signals on the PCB. Why don't you go for a FPGA or on the Wordclock board for a CPLD (XC9572XL)? Would make your life much easier and you can get ride of a lot of jumpers.

I only saw 100nF caps but by driving "heavy" loads where does the energy came from. First from the 100nF right but than?? You only have a 2 layer board and you will need at least 2 or better 3 of 10uF Tantalum. One right at the connector and the others around on the board.


From MCS:
Wordclock should be an Ethernet-like bus with T-connectors and a terminator at the end - but I don't know. You would need a terminator when the input is not used, but I guess most people have some Ethernet terminators available...

I'm not sure the four outputs need buffers - my board works fine without at least. But the bitclock, wordclock and masterclock do of course.

I normally like to put ground pins between the signals on the headers to keep them from interfering (a la SCSI). I actually use 10-pin connectors with a lot of ground pins. But that's mostly because cables with 10-pin IDC connectors are so easy to make.

Here's my tested OptoGen schematic BTW: http://stiftsbogtrykkeriet.dk/~mcs/OptoGen_sch.gif